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Altera_Forum's avatar
Altera_Forum
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10 years ago

Problem with VIP suite on Cyclone V device

Hello,

I am trying to work with VIP suite. My main objective is to read YCbCr 4:2:2 progressive 720x576 image from HPS DDR3 into the VIP suite using Frame reader , interlace the frame reader output , serialize the output and send it to ADV chip using CVO. I'm running the VIP IPs at 27Mhz and the memory read is at 216Mhz.

I tested this flow HPS DDR3->FR->ITL->CVO using the VIP, underflow in CVO output detected with non valid image output.

To check the path error I have put signal tap into the project and suspected Interlacer output.

I tried using test pattern generator , TPG(YcbCr,4:2:2,sequence,interlaced output)->CVO I get proper color pattern output.

I then tried , TPG(YcbCr,4:2:2,progressive,parallel)->ITL->CPS->CVO , I get CVO underflow and the output image is not proper.

Can anyone tell me the correct usage of Interlacer IP ? I read in the VIP userguide that it works with odd heights of the image?If it is so how can i go about getting a valid output? Any leads would be greatly appreciated.

Thankyou and Regards,

Vidya

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  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    In the first post of the thread, you mentioned:

    --- Quote Start ---

    I tried using test pattern generator , TPG(YcbCr,4:2:2,sequence,interlaced output)->CVO I get proper color pattern output.

    --- Quote End ---

    My suggestion would be to briefly retest that configuration and confirm that no distortion appears. If that configuration works well, it would point toward the addition of ITL+CPR blocks causing the issue.

    If TPG->CVO has the same distortion, then the issue is probably with the CVO not matching your hardware/display.

    Good luck.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    The interlacer core creates an interlaced output by dropping every other line in the incoming progressive frames. So the interlacer output field rate is equal to the progressive frame rate, but the data rate is cut in half. If you're running the ITL and CVO cores at the same clock rate then the CVO pretty much has to underflow. The CVO is driving a display so it can't be starved. Your pipeline works with the TPG because the TPG is generating interlaced fields natively instead of taking in a progressive frame and discarding every other line (which means the CVO core input is starved 50% of the time). If you run the ITL core at 2x the CVO core clock rate the pipeline should work.

    By the way, color bars is a bad test pattern to evaluate interlacing because every row of the test pattern is identical. You should try it with a pattern that has some variation vertically.

    One other point. You could interlace properly (meaning that each progessive frame produces two interlaced fields) by perferming the interlacing on the way out of DDR3. Just read even lines out of the frame buffer to produce even fields then odd lines to produce odd fields. This would require some custom logic to read the fields from memory, but then you could feed data directly to the CVO.
  • Altera_Forum's avatar
    Altera_Forum
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    10 years ago

    Thank you very much rsefton and Ted.

    The test pattern generator output works fine with the pipeline running @54Mhz and the CVO pixel clock @27Mhz.

    The distortion or artifact was because of the display device, I changed the display device and the output looks perfectly fine.

    Now I shall proceed to testing with frame reader and mixer.

    Regards,

    Vidya