Agilex 7 R-Tile CXL IP: D2H write bandwidth does not scale with dual CAFU AXI-MM ports

Device: Agilex 7 I-Series AGI027

Software: Quartus Prime Pro 24.3

IP Core: CXL Type 2 IP

Issue Description:

We are attempting to increase CXL Device-to-Host (D2H) write bandwidth by utilizing both CAFU AXI-MM ports (port 0 and port 1) provided in the CXL Type 2 IP design example. However, our measurements show that enabling both AXI ports does not improve bandwidth as expected. For Non-cacheable writes, bandwidth remains unchanged when moving from one port to two ports. For Cacheable Owned writes, bandwidth decreases when using two ports. Please refer to the figures blow for detailed results.

We are using the design example configured with two DCOH slices. To avoid potential DCOH contention, we've implemented address interleaving such that:

- AXI port 0 only accesses addresses corresponding to "even number × 64B"

- AXI port 1 only accesses addresses corresponding to "odd number × 64B"

Despite this, no bandwidth improvement is observed for either Non-cacheable or Cacheable Owned traffic.

Additionally, the non-cacheable bandwidth curve remains almost identical regardless of whether one or both AXI ports are used. This suggests that the exercised hardware path may contain a bottleneck or contention point within (either soft or hard part of) the CXL Type-2 IP.

We would like to understand how to resolve this bandwidth limitation. If it cannot be improved, we would appreciate clarification on the underlying cause of this behavior.

Thank you for your time and support.