Problem with VIP suite on Cyclone V device

The interlacer core creates an interlaced output by dropping every other line in the incoming progressive frames. So the interlacer output field rate is equal to the progressive frame rate, but the data rate is cut in half. If you're running the ITL and CVO cores at the same clock rate then the CVO pretty much has to underflow. The CVO is driving a display so it can't be starved. Your pipeline works with the TPG because the TPG is generating interlaced fields natively instead of taking in a progressive frame and discarding every other line (which means the CVO core input is starved 50% of the time). If you run the ITL core at 2x the CVO core clock rate the pipeline should work.

By the way, color bars is a bad test pattern to evaluate interlacing because every row of the test pattern is identical. You should try it with a pattern that has some variation vertically.

One other point. You could interlace properly (meaning that each progessive frame produces two interlaced fields) by perferming the interlacing on the way out of DDR3. Just read even lines out of the frame buffer to produce even fields then odd lines to produce odd fields. This would require some custom logic to read the fields from memory, but then you could feed data directly to the CVO.