Problem simulating FFT IP core
Hi all,
I am trying to simulate the FFT IP core using cocotb.
I have the FFT setup as a 128 point, variable streaming, fixed point FFT with 12 bit natural input and 20 bit bit-reverse output.
I have successfully exported the IP core from quartus megawizard, compiled it using Questasim, and linked it without any issues. I have followed the instructions about input flow control, and I believe I am controlling the values of sink_sop, sink_valid, etc. correctly.
However, when I run the simulation, it keeps crashing with an underflow error.
# ** Fatal: (vsim-3421) Value -1 is out of range 0 to 7.
# Time: 570 ns Iteration: 2 Process: /fft_ip_0430/fft_ii_0/auk_dspip_r22sdf_top_inst/r22sdf_core_inst/gen_natural_order_core/gen_stages(3)/r22_stage/processing_cnt_p File: C:/intelFPGA_lite/23.1std/quartus/libraries/custom/fft_ip_0430/fft_ip_0430/simulation/submodules/mentor/auk_dspip_r22sdf_stage.vhd Line: 1002
# Fatal error in Process processing_cnt_p at C:/intelFPGA_lite/23.1std/quartus/libraries/custom/fft_ip_0430/fft_ip_0430/simulation/submodules/mentor/auk_dspip_r22sdf_stage.vhd line 1002
I've attached the fft toplevel, python testbench, Makefile and the waveform file of the simulation in 'simfiles_20240105.zip' to this post for more detailed insights. I am wondering if anyone here has experience with simulating the FFT IP core and might be able to suggest what could be causing this error or how to resolve it. Any tips or advice would be greatly appreciated!
Thanks in advance for your help!
Marnix