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Altera_Forum's avatar
Altera_Forum
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15 years ago

problem Master LCD of Read/write in cyclone II with vhdl

hello,

i would to create my master of read and write in LCD in the cyclone II

but before start write and read i would write the code of

Initialization of the LCD in cyclone II with VHDL.

this is the code of initilizate LCD with C

void LCD_Init()

{

lcd_write_cmd(LCD_16207_0_BASE,0x38);

niosleep();

lcd_write_cmd(LCD_16207_0_BASE,0x0C);

niosleep();

lcd_write_cmd(LCD_16207_0_BASE,0x01);

niosleep();

lcd_write_cmd(LCD_16207_0_BASE,0x06);

niosleep();

lcd_write_cmd(LCD_16207_0_BASE,0x80);

niosleep();

}

so if somebody have already this pb ?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi, if I have understood, You want to write a VHDL code for Initialization of the LCD, don't you ?

    If yes, you have to design a short sequential logic (with counters in order to make temporisation) which will be a Finite State Machine, but a quite simple one.

    But where is the problem of using LCD_Init() ?

    You call LCD_init() at the begining of your main programm.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    hello,

    yes i wrote a code vhdl for initilization of LCD ,

    i send the value of initilization one after one using state machine and process

    but when i would tried in simulation or in cyclone II no result

    but if i inderstand for your reponse i can use the function lcd_init()

    in vhdl code ?

    because i would have custom IP (master of read & write ) in LCD
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Is your LCD OK ?

    I guess you use 2*16 chararacter Text LCD.

    LCD takes approx. 40 ms to "boot up".

    In your state machine, when you send init. commands, you must either wait for a time (2ms but it depends of the LCD) or for a busy signal.

    Make sure of your control signal : LCD_Rw, LCD_en...

    Make sure of your inout LCD_data bus and control signal on this.

    Make sure of your init. commands : your sequence. I have a doubt on what you are posted.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    hello,

    yes i work with The Optrex 16207 LCD in the cyclone II

    for all signal of controller LCD i attached in the top level this is

    LCD_ON <='1';

    LCD_BLON <= '1';

    component_sopc_LCD :sopc_LCD

    port map (

    LCD_E_from_the_lcd_0 => LCD_EN,

    LCD_RS_from_the_lcd_0 => LCD_RS,

    LCD_RW_from_the_lcd_0 => LCD_RW,

    LCD_data_to_and_from_the_lcd_0 =>LCD_DATA,

    .......

    );

    i don't know if you inderstand my question is : i would create a Master who write and read in the LCD !the pb of initialzation of lcd ??

    you find a code who i wrote attached to this replyhttps://www.alteraforum.com/forum/attachment.php?attachmentid=2738
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi, you speak French :)

    Your English writing is not very good.

    We continue to write in English so that others can understand.

    You don't have a reset signal and/or a RAZ. i suggest you to add reset signal. 

    process (reset_n, clk)
begin
if reset_n = '0' then
-- all init here
elsif rising_edge(clk) then
-- all synchronous signal here
end if;
end process;

    One of good coding style is to not make Initialization in signal declarations because of synthesis tool.

    Minor : when you declare "integer", better is to specify "integer range 0 to 250" for ex.

    maybe your proc_state is not initialize to '0'

    Major : You have to be most rigorous when writing process : in line 111 (--process pour l'initialisation envoie sequentiel des données) you should write "process(g_clk)"

    Amicalement,