problem Master LCD of Read/write in cyclone II with vhdl

Hi, you speak French :)

Your English writing is not very good.

We continue to write in English so that others can understand.

You don't have a reset signal and/or a RAZ. i suggest you to add reset signal.

process (reset_n, clk)
begin
if reset_n = '0' then
-- all init here
elsif rising_edge(clk) then
-- all synchronous signal here
end if;
end process;

One of good coding style is to not make Initialization in signal declarations because of synthesis tool.

Minor : when you declare "integer", better is to specify "integer range 0 to 250" for ex.

maybe your proc_state is not initialize to '0'

Major : You have to be most rigorous when writing process : in line 111 (--process pour l'initialisation envoie sequentiel des données) you should write "process(g_clk)"

Amicalement,