port assignment in vhdl

http://www.electronicdesignworks.com/advanced_digital_electronics/introduction/introduction.htm

An in port represents an external input to your logic. It can't be driven internally. What do you want to achieve?

thanks for replies.i am trying to debug my VHDL program, i use a simulator for this.how can i give values to in port for debuging?

In a simulator, the design under test will be instantiated in a testbench. There you can drive input and inout ports and also force internal signals, if necessary.

thank you, i will try to do UUT issue in the simulator.