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Altera_Forum's avatar
Altera_Forum
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14 years ago

port assignment in vhdl

hi all, i am new to VHDL and this question may be easy for you.my question is: how can i assign value to an in port?my port declaration is: DATA_I : in std_logic_vector(7 downt...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

thanks for replies.i am trying to debug my VHDL program, i use a simulator for this.how can i give values to in port for debuging?