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Altera_Forum
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14 years ago

port assignment in vhdl

hi all, i am new to VHDL and this question may be easy for you.my question is: how can i assign value to an in port?my port declaration is: DATA_I : in std_logic_vector(7 downt...
Altera_Forum's avatar
Altera_Forum
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14 years ago

In a simulator, the design under test will be instantiated in a testbench. There you can drive input and inout ports and also force internal signals, if necessary.