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Altera_Forum's avatar
Altera_Forum
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14 years ago

pll inclk from internal logic

In my design i want to generate a clock using an internal logic and then insert it to a PLL to multiply it by n.

i understand a pll must get an input clock from a gclk or another pll or an internal logic using a clock control block.

tried it in quartus but got the following error:

Error: Clock input port inclk[0] of PLL "pll_125m:pll_125m_altpll|altpll:altpll_component|pll_125m_altpll:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block

Info: Input port INCLK[0] of node "pll_125m:pll_125m_altpll|altpll:altpll_component|pll_125m_altpll:auto_generated|pll1" is driven by control_block:control_block|control_block_altclkctrl_uhi:control_block_altclkctrl_uhi_component|wire_clkctrl1_outclk which is OUTCLK output port of Clock control block type node control_block:control_block|control_block_altclkctrl_uhi:control_block_altclkctrl_uhi_component|clkctrl1

Error: Port(s) inclk[0] of Clock Control Block "control_block:control_block|control_block_altclkctrl_uhi:control_block_altclkctrl_uhi_component|clkctrl1" must be used

can you please help me understand what is the problem?

Best,

carmi

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Even those FPGAs, that allow PLLs to be driven by global clock nets don't offer the option to use a logic generated clock as PLL inclock, see e.g. the Cyclone IV hardware handbook:

    --- Quote Start ---

    This input port is fed by a pin-driven dedicated GCLK, or through a clock control block if the clock control block is fed by an output from another PLL or a pin-driven dedicated GCLK. An internally generated global signal cannot drive the PLL.

    --- Quote End ---

    P.S.: A similar statement from the Stratix IV handbooK:

    --- Quote Start ---

    Stratix IV device PLLs cannot be driven by internally generated GCLKs or RCLKs. The input clock to the PLL has to come from dedicated clock input pins or pin/PLL-fed GCLKs or RCLKs only.

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    thanks,

    what do they mean by internal logic as an input the the ppls?

    is this logic connects the pll outputs to the inclk in another pll only?

    what is the reason that i can't connect a clock from an internal logic to a pll?

    and in case i need to create the clock myself ,i couldn't find in the cyclon 3 datasheet jitter specification for an internal clock in the design. this clock used by hardware and not by memory or other plls.

    thanks