pll inclk from internal logic

Even those FPGAs, that allow PLLs to be driven by global clock nets don't offer the option to use a logic generated clock as PLL inclock, see e.g. the Cyclone IV hardware handbook:

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This input port is fed by a pin-driven dedicated GCLK, or through a clock control block if the clock control block is fed by an output from another PLL or a pin-driven dedicated GCLK. An internally generated global signal cannot drive the PLL.

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P.S.: A similar statement from the Stratix IV handbooK:

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Stratix IV device PLLs cannot be driven by internally generated GCLKs or RCLKs. The input clock to the PLL has to come from dedicated clock input pins or pin/PLL-fed GCLKs or RCLKs only.

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