Forum Discussion
New ContributorPCIe stuck at reset Agilex5
Hi Altera Team,
I'm trying to get PCIe connection working on our custom board. We had some problems with our design. Reset pin (CF128) is connected to CF121 on board (we forgot to connect it). At the start i set CF121 to '1', to get PCIe out of reset. When fpga boots, all clocks should be up and stable.
Based on "Link Training Debugging Flow" my IP core is in reset and i should check pin_perst_n.
Pin is set to '1', but IP is still in reset?
What could be the couse?
Is there a chance for this behaviour if core can't detect root?
Do i need IO_Pll to lock for core to get out of reset?
I use example design for PCIe, with different pinout.
Device: A5ED065BB32AE6S - Common clock architecture
1 Reply
MateuszZThe problem was lock signal from IO Pll. Reset IP was holding core in reset. I have this clock figured out on my final design, but not on example.
My bad
I didn't expect this dependency
Problem solved
