Forum Discussion

corestar's avatar
corestar
Icon for Contributor rankContributor
2 years ago
Solved

PCIe pld_clk conflicting coreclkout statements

I'm using a Cyclone V GT with PCIe ST core. The app works fine when I drive pld_clk with coreclockout, but fails when I drive pld_clk with a 150 MHz external clock. I used 150 MHz instead of 125 MHz ...
Pcie
  • VenT_Altera's avatar
    VenT_Altera
    2 years ago

    Hi @corestar,


    Thanks for sharing your objective.

    My apologies for the delayed response, I took some time to gather the information.


    In this case, it is suggested that you drive the pld_clk with coreclkout_hip, as using a single clock simplifies timing.


    In the situation that you wish to drive the pld_clk with an other clock source, the following clock frequencies of the clock source could be used:

    1.When coreclkout_hip is 62.5 MHz:

    Try to use 125 MHz, or 250 MHz.

    2. When coreclkout_hip is 125 MHz:

    Try to use 250 MHz.

    Please note that not all frequencies of other clock source within the specified range can be used to drive the pld_clk.


    Thanks.

    Best Regards,

    VenTingT


VenT_Altera's avatar
VenT_Altera
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi @corestar,


Thank you for your feedback. I will forward it to our internal team for review and necessary updates to the documentation.


I’m glad that your question has been addressed. I now transition this thread to community support. If you have a new question, please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed or response within the next 15 days to allow me to continue to support you. After 15 days, this thread will transition to community support. The community users will be able to help you with your follow-up questions.


Thanks.

Best Regards,

VenTingT


p/s: If any answers from the community or Intel support are helpful, please feel free to mark them as solutions, give them kudos, and rate 4/5 for the survey.