corestar
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Re: How is PCIe coreclkout_hip generated?
Hello, It's still not very clear how all this works, but apparently the information, such as jitter and accuracy of coreclock, is not available for some reason. Please go ahead and close the ticket. Just as a side note, Timing Analyzer does in fact report coreclockout as a separate clock to the incoming PCIe_ref clock pin (as opposed to one generated by it).Re: How is PCIe coreclkout_hip generated?
@Wincent_Altera Thanks for the info. If they can really generate a stable low jitter clock inside the FPGA, it would be really useful to make that available independent of the PCIe core. For now, I think the safest route is to just use an external clock source to drive most of the FPGA logic and coreclockout_hip for the PCIe. Lots of clock domain crossings but so be it. Thanks, DaveRe: How is PCIe coreclkout_hip generated?
Hello, Yes you are correct, the coreclkout_hip source is from PCIe HIP. Are you saying the PCIe HIP has a clock generator independent of incoming PCIe refclk? Are there any specs on it's jitter and accuracy? I'm thinking of using it instead of an external clock. I'm familiar with the PCIe jitter specs, but if the coreclockout_hip is generated from refclk, I was wondering about the situation where PCIe Spread Spectrum is enabled (the norm on many systems) as described here: PCIe Spread Spectrum Clocking In this case, refclk is modulated with a 35 KHz triangle wave and the incoming PCIe refclk itself has very high jitter. Apparently has high as 4ns. This is on purpose to reduce EMI. The PCIe IP itself is designed to handle it, but other parts of a system are not and depend on low jitter. ThanksHow is PCIe coreclkout_hip generated?
I'm using a Cyclone V GT PCIe Avalon ST core. It might be helpful to use coreclkout_hip to run our application layer, but it is not clear how that clock is generated and how much jitter it has. I had assumed this clock was generated from the 100 MHz refclk. But in spread spectrum mode, the default (to reduce EMI) on the processor we are using, the refclk can have enormous jitter. I assume the hard IP deals with the on the Phy side, but if coreclkout_hip is generated from refclk, does it clean the jitter? But looking at Figure 6-4 in the "Cyclone V Avalon ST User Guide", it shows: It looks like refclk and coreclkout_hip are not related. I realize this is just a block diagram, but if coreclkout_hip is not generated from refclk, how is it generated? I there a clock source in the PCIe hard IP? And much jitter does it have?PCIe pld_clk conflicting coreclkout statements
I'm using a Cyclone V GT with PCIe ST core. The app works fine when I drive pld_clk with coreclockout, but fails when I drive pld_clk with a 150 MHz external clock. I used 150 MHz instead of 125 MHz since it says you must use a 0 ppm accuracy clock at 125 MHz and I don't know how to do that! According to "Cyclone V Streaming Interface for PCIe Solutions User Guide", I should be able to do this (Table 4-5): But according to "Cyclone V Hard IP for PCI Express User Guide": This seems contradictory. And the latter seems wrong since if you must drive it with coreclkout, why did they not just do that internally? So can I drive pld_clk from a PLL? This would save alot of clock domain crossing inside my App.
