PCIe MSI interrupt

Hi,

Thanks for your reply.

Below mentioned our procedure we are following to test MSI interrupt, but we didn't get the expected output.

1. Reading Config space register with offset 0x50

Offset : 0x50 Value : 25522181(decimal)

Here bit[16] set as 1 to enable MSI interrupts

2. Reading Config space register with offset 0x4

Offset : 0x4 Value : 1048582(decimal)

Here bit[10] is disable , bit[1] (Memory space) and bit[2] (Bus Master) are 1.

When link is down:-

root@localhost:~# cat /proc/interrupts | grep fpga

65: 0 0 0 0 0 0 0 0 PCI-MSI 3670016-edge fhgw_fpga_drv

When link is up:-

root@localhost:~# cat /proc/interrupts | grep fpga

65: 0 0 0 0 0 0 0 0 PCI-MSI 3670016-edge fhgw_fpga_drv

Please find the test log in attached file.

Hi,

We are using AVMM interface. Following steps are followed to read MSI interrupt.

1. Set MSI Enable of MSI Control register, this bit is mapped to bit[16] of offset 0x50 in configuration space register.
2. Set Interrupt Disable bit[10] of Command register at configuration space offset register 0x4 to disable legacy interrupt.
3. Set bit[1] (Memory space) and bit[2] (Bus Master) of Command Register at configuration space offset register 0x4 to enable the ability to generate MSI message.

But in our case interrupt is not generate.

When link is down:-

root@localhost:~# cat /proc/interrupts | grep fpga

65: 0 0 0 0 0 0 0 0 PCI-MSI 3670016-edge fhgw_fpga_drv

When link is up:-

root@localhost:~# cat /proc/interrupts | grep fpga

65: 0 0 0 0 0 0 0 0 PCI-MSI 3670016-edge fhgw_fpga_drv

For your reference our PCIE IP configuration snapshot in below. Please check if there is any configuration missing from our PCIE IP.

Regards,

Nandhakumar