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Sudhirkv's avatar
Sudhirkv
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5 years ago

PCIe MSI interrupt

Hi, We are working on a custom board using the fpga stratix. In this device data communicates using the PCIE protocol. Please find the below our PCIE FPGA ip core configuration snapshot. In this w...
  • Sudhirkv's avatar
    Sudhirkv
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi,

    Thanks for your reply.

    Below mentioned our procedure we are following to test MSI interrupt, but we didn't get the expected output.

    1. Reading Config space register with offset 0x50

    Offset : 0x50 Value : 25522181(decimal)

    Here bit[16] set as 1 to enable MSI interrupts

    2. Reading Config space register with offset 0x4

    Offset : 0x4 Value : 1048582(decimal)

    Here bit[10] is disable , bit[1] (Memory space) and bit[2] (Bus Master) are 1.

    When link is down:-

    root@localhost:~# cat /proc/interrupts | grep fpga

    65: 0 0 0 0 0 0 0 0 PCI-MSI 3670016-edge fhgw_fpga_drv

    When link is up:-

    root@localhost:~# cat /proc/interrupts | grep fpga

    65: 0 0 0 0 0 0 0 0 PCI-MSI 3670016-edge fhgw_fpga_drv

    Please find the test log in attached file.