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Sudhirkv's avatar
Sudhirkv
Icon for New Contributor rankNew Contributor
5 years ago

PCIe MSI interrupt

Hi, We are working on a custom board using the fpga stratix. In this device data communicates using the PCIE protocol. Please find the below our PCIE FPGA ip core configuration snapshot. In this w...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Nandhakumar,


From the End point, if the Interrupt Enable Register at address 0x50 in CRA, bit15:0 (Control by Host) and RxmIrq_i [15:0] value are set to 1, you should be able to see the MSI request signal. If the MSI request signal is high but not observed in the host, you may consider to use protocol analyzer to check if the host not recognize the MSI request or the end point does not actually send the MSI request.


Thanks

Best regards,

KhaiY