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Sudhirkv's avatar
Sudhirkv
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5 years ago

PCIe MSI interrupt

Hi, We are working on a custom board using the fpga stratix. In this device data communicates using the PCIE protocol. Please find the below our PCIE FPGA ip core configuration snapshot. In this w...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Nandhakumar,


What device and Avalon interface (Avmm or Avst) you are using? Could you explain how do you trigger the MSI in details?


Thanks

Best regards,

KhaiY


Sudhirkv's avatar
Sudhirkv
Icon for New Contributor rankNew Contributor
5 years ago

Hi,

We are using AVMM interface. Following steps are followed to read MSI interrupt.

  1. Set MSI Enable of MSI Control register, this bit is mapped to bit[16] of offset 0x50 in configuration space register.
  2. Set Interrupt Disable bit[10] of Command register at configuration space offset register 0x4 to disable legacy interrupt.
  3. Set bit[1] (Memory space) and bit[2] (Bus Master) of Command Register at configuration space offset register 0x4 to enable the ability to generate MSI message.

But in our case interrupt is not generate.

When link is down:-

root@localhost:~# cat /proc/interrupts | grep fpga

65: 0 0 0 0 0 0 0 0 PCI-MSI 3670016-edge fhgw_fpga_drv

When link is up:-

root@localhost:~# cat /proc/interrupts | grep fpga

65: 0 0 0 0 0 0 0 0 PCI-MSI 3670016-edge fhgw_fpga_drv

For your reference our PCIE IP configuration snapshot in below. Please check if there is any configuration missing from our PCIE IP.

Regards,

Nandhakumar