PCIe Hard IP - Can 'valid' De-assert Between SOP and EOP During DMA Read Completion?

Hi Wincent_Altera​ 

Thanks for your response. I have gone through the references you provided.

In the first link, the explanation mainly about application-side throttling when PCIe acts as the source. However, my concern is whether the PCIe IP itself can throttle the bus while transmitting data(Source), particularly during DMA operations.

I also reviewed the interface section in the second reference. It similarly mentions only application-level throttling, and I could not find any details indicating whether the PCIe core independently throttles the bus, or under what conditions it might do so.

Could you please clarify if the PCIe IP has any mechanism to throttle the bus during DMA transfers(when PCIe act as a source), or if throttling is entirely controlled by the application logic?