New Contributor
New ContributorThanks for your response. I have gone through the references you provided.
In the first link, the explanation mainly about application-side throttling when PCIe acts as the source. However, my concern is whether the PCIe IP itself can throttle the bus while transmitting data(Source), particularly during DMA operations.
I also reviewed the interface section in the second reference. It similarly mentions only application-level throttling, and I could not find any details indicating whether the PCIe core independently throttles the bus, or under what conditions it might do so.
Could you please clarify if the PCIe IP has any mechanism to throttle the bus during DMA transfers(when PCIe act as a source), or if throttling is entirely controlled by the application logic?
Regular ContributorHi Abhi_Krishnan_R ,
In normal operation of PCIe IP design example provided by Altera , the throttle/bubble is not a normal operation. Regarding throttling based on my experience and understanding on RX (PCIe → user), throttling is governed by your application through rx_st_ready. The PCIe HIP does not arbitrarily throttle mid‑packet while ready remains asserted; it responds to backpressure and streams at the interface clock rate otherwise.
If you want to stress the design, I would suggest to de‑assert rx_st_ready for arbitrary spans within a TLP and verify proper resume to EOP. To be honest I do not have any exact answer as this is something customize and I never try before, Hope my suggestion able to help you to move a step forward.
Regards,
Wincent
