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New Contributor

1 day ago

PCIe Hard IP - Can 'valid' De-assert Between SOP and EOP During DMA Read Completion?

Product / IP: Intel PCIe Hard IP (Avalon-ST Interface Device Family: Cyclon 10 GX Reference Manual: https://docs.altera.com/r/docs/683647/18.0/arria-10-and-cyclone-10-gx-avalon-streaming-interfac...

Pcie

Transceiver

Wincent_Altera

Regular Contributor

3 hours ago

Hi Abhi_Krishnan_R ,

For the behaviour of rx_st_eop/sop. I think you can refer below document as a reference
https://docs.altera.com/r/docs/683059/25.1.1/p-tile-avalon-streaming-fpga-ip-for-pci-express-user-guide/avalon-st-rx-interface-rx_st_ready-behavior

For C10 device, you may check under AVST interface section
https://docs.altera.com/r/docs/683647/18.0/arria-10-and-cyclone-10-gx-avalon-streaming-interface-for-pci-express-user-guide/interfaces-and-signal-descriptions

Regards,
Wincent_Altera

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