PCIe Enumeration Failure for CXL IP

If possible, please follow UG section "6.1. Recommended Hardware Setup" using an Intel platform for the test.

Unfortunately, we do not have an Intel platform. Was the CXL IP ever tested with non-Intel platforms?

Follow section 6.3 to use pof to boot FPGA. This step is necessary for CXL.

We have programmed the board to the non-volatile memory successfully using both a POF and JIC file. The files tested were the pre-compiled binaries for the SOF/POF, and the JIC was generated from the pre-compiled SOF binary. Additionally, we compiled our own example designs to generate SOF, POF, and JIC. Configuration was verified for each test for both volatile and non-volatile memory. All tests failed in the same manner as described above.

Is there a specific reason why the CXL IP requires the configuration image be located in the flash? Our system boots the FPGA board fully before the host server is booted, so there is no timing contention.

Can you provide any additional support on what could be causing enumeration failure or steps that can be used to debug the cause?