Forum Discussion

danield17's avatar
danield17
Icon for New Contributor rankNew Contributor
4 months ago

PCIe and Scaler II IPs

Hi,

I’m working on a project that transfers an image via PCIe to a Scaler II IP, processes it, and then sends it back to the host computer.

My initial plan was to connect the PCIe IP to two mSGDMA IPs (configured for MM-to-ST and ST-to-MM), with the Scaler II IP on the other side.

The image is in RGB format, meaning 8 bits per symbol and 3 symbols per pixel. Based on this configuration, the Scaler II IP’s streaming input and output interfaces expect a 192-bit data width. However, the mSGDMA IPs are set to 1024 bits, and the Avalon Streaming Adapter IP cannot be used to adapt between these widths.

Does anyone have suggestions for connecting the Scaler II IP to the PCIe IP in this situation? I’m open to changing the current architecture, but I need a high-performance way to transfer data from PCIe to the Scaler II IP and back.

I’m working with an Agilex 7 I-Series device, using the AXI MCDMA IP to interface with the BAM and BAS ports.

Pcie

3 Replies

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    4 months ago

    Hi Danield,


    Thanks for reaching out.


    Allow me some time to investigate your issue. I shall come back to you with the findings.

    As you are using Agilex 7 I-Series, are you using F-Tile or R-Tile? Do you need to use the MCDMA IP, or can you switch to the F/R-Tile AVST IP?


    Thanks.

    Best Regards,

    Ven


    • danield17's avatar
      danield17
      Icon for New Contributor rankNew Contributor
      4 months ago

      Hi Ven,

      I’ve already found a solution.

      To answer your questions:

      • I’m using the R-Tile.
      • I didn’t specifically need the MCDMA. my goal was to find a solution that works regardless of the device or PCIe IP being used.
      • I preferred sticking with a PCIe IP that supports a memory-mapped interface, as I find it more flexible and convenient.

      The solution I settled on was transferring the image to an EMIF and connecting two Frame Buffer II IPs to it. one configured as a Frame Reader to send the image to the video IPs, and the other as a Frame Writer to return the processed image from the video IPs back to the EMIF.

      Best regards,
      Daniel

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    4 months ago

    Hi Danield,


    Thank you for the update and for sharing your solution.


    As there are no further inquiries, I will transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desired request, and post a feed/response within the next 15 days to allow me to continue to support you.


    If you require any support with the Frame Buffer II and EMIF IP integration, you are welcome to post a new forum thread. Someone will be right with you.


    Thanks.

    Best Regards,

    Ven