Forum Discussion
New ContributorOver 4GB PCIe BAR Size Issue
New ContributorHi Ven,
1. I'm using my own application, which I'm confident is functioning correctly. Through it, I read from BAR2 at the EMIF offset.
2. In the failure scenario, the values I read were all 0xFFs. Even after attempting to write to the same offset, I continued to read only 0xFFs.
3. When the parameter was unchecked, I could only read/write successfully if the BAR size was set to 2GB.
4. Read and write operations only worked when burst capability was enabled. I also tried using other BARs and encountered the same issue as with BAR2 when burst was disabled.
Regards,
Daniel
Regular ContributorHi Daniel,
The DMA master interface is also connected to the EMIF, and with DMA, both reads and writes work as expected. But with the BAR2 master, it didn’t work.
>> Do you have any log or .stp showing failure vs passing scenario ?
>> With that, we can better understand how the fail behave.
I'm using my own application, which I'm confident is functioning correctly. Through it, I read from BAR2 at the EMIF offset.
>> do you ever try out the design example that we provided https://www.intel.com/content/www/us/en/design-example/714464/intel-arria-10-fpga-an708-pcie-3-0-x8-avalon-memory-mapped-direct-memory-access-dma-with-external-memory-design-example.html
>> If not, maybe you can try that and see if the same scenario happen (ONLY if you have time, else we can continue debug your design). BUT , trying that will help to narrow down where the fail coming from and help to accelerate our debug progress - I left the decision back to you.
Read and write operations only worked when burst capability was enabled. I also tried using other BARs and encountered the same issue as with BAR2 when burst was disabled.
>> is it compulsory for your design to disable the burst mode ?
Additional information
>> Based on my experience IF the Avalon bus implementation does not use the burst. When the memory controller receives a read transaction but the number of write data beats does not match what has been indicated by the busrtcount signal then I assume it will wait for more write data before processing the read.
>> That could be the reason why you seeing those delay.
Regards,
Wincent_Altera
