Forum Discussion
6 Replies
- Alberto_Sykes
Occasional Contributor
praveenkumar, Thank you for posting in the Intel® Communities Support.
In order for us to be able to provide the most accurate assistance on this matter, I will transfer your thread to the proper department so they can assist you with this topic as soon as possible.
Regards,
Albert R.
Intel Customer Support Technician
A Contingent Worker at Intel
- sstrell
Super Contributor
Supported numbers are shown here:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ds/ds_nios2_perf.pdf
If you can't run it faster than 100 MHz, then there may be other timing issues in your design. Have you created a .sdc file and performed timing analysis?
- praveenkumar
Occasional Contributor
Thanks for reply,
in the thread which you provided can't find regarding cyclone iii .
can u assist with the timing analysis and also dma interrupt mechanism .
i have to receive 24 bytes using uart with dma .
Regards
praveen kumar
- sstrell
Super Contributor
The numbers in the document don't really matter. What matters is that your design meets timing requirements for the device, which is what timing analysis is for. Again, do you have a .sdc file? Did you perform timing analysis to see what path(s) might be failing timing?
If you need help, you can get started with this training:
https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html
- BoonBengT_Altera
Moderator
Hi praveenkumar,
Hope this message find you well and good day, as suggestion has been provided and further actions will be taken.
Hence with that we would be closing this case and if further queries required, please feel free to open a separate post and we would be more than happy to get back to you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
Warm regards
BB