Forum Discussion
Occasional ContributorNios II/e Core maxm clock
Super ContributorSupported numbers are shown here:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ds/ds_nios2_perf.pdf
If you can't run it faster than 100 MHz, then there may be other timing issues in your design. Have you created a .sdc file and performed timing analysis?
- praveenkumar
Thanks for reply,
in the thread which you provided can't find regarding cyclone iii .
can u assist with the timing analysis and also dma interrupt mechanism .
i have to receive 24 bytes using uart with dma .
Regards
praveen kumar
- sstrell
The numbers in the document don't really matter. What matters is that your design meets timing requirements for the device, which is what timing analysis is for. Again, do you have a .sdc file? Did you perform timing analysis to see what path(s) might be failing timing?
If you need help, you can get started with this training:
https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html
- praveenkumar
Thank you for reply .
i will get back to you after the training session for further queries
