Honored ContributorHi. I am trying to use the NCO to generate the sine waveform. However, the waveform obtained is different where it is attached. May i know where to modify it in order to get the correct the sine waveform?
FYI, i chose the parellel CORDIC algorithm to generate sine waveform. Spec: Phase Acc: 32 Angular Position: 16 Magnitude Precision: 16 Clock rate: 50M desired freq: 1M phi_inc_i: 85899346 Thanks
Honored ContributorNCO output is fine, change your display format to "signed decimal".
Honored Contributorit works. Thanks a lot
Honored ContributorDid you add noise to the waveform? Apart from signed/unsigned issue, the signal quality looks rather poor.
Honored ContributorI add some minimum of phase dithering into the signal. The signal is slightly improved.
There result confuses me on the output. The result change state before the rising clock. Besides, i add a register output, the output still change before rising edge. I am pretty sure that the transition state is on rising edge of the clock because i do functional simulation on it Can someone explain to me? Thanks a lotHonored ContributorAre you sure, that the transition isn't caused by the previous rising clock edge? Run the design at a lower clock frequency for clarity.
Honored ContributorI have run the low freq simulation which is 25M clk. It is fine. However, if i run at the 125M, it violates.
any reason to cause this? ThanksHonored ContributorI guess, your CORDIC implementation has to be pipelined to achieve the intended performance. The problem should show up also in timing analysis, e.g. the classical timing analyzer would clearly detect it, because it's a rather simple single clock domain problem. You have to modify the CORDIC core implementation, until the timing violations are gone.
Honored Contributorwhy do not use modesim
Honored ContributorFvM,
I can't modify the CORDIC algorithm since i use the NCO provided in Megafunction. Besides, i try to use multiplier as a algorithm to replace CORDIC, the problem still exists. Fourier, As you propose, i try to simulate it on modelsim Altera, i get an error on: Error: Can't generate netlist output files because the file "E:/Quartus II Project/Waveform/Sin_Cos_Wave/Parellel_CORDIC/sin_10_8/sin25MHz/incremental_db/compiled_partitions/sin_10_8_25MHz.root_partition.map.atm" is an OpenCore Plus time-limited file Any idea to solve it in order to simulate in Modelsim? ThanksHonored ContributorI can't recognise any problems from your pictures. I expect the output to transition after the clk edge. That is what it does but gets close in front of next clk edge(Tco of register is several ns) such that you think it changes before clk edge.
