Honored ContributorHi. I am trying to use the NCO to generate the sine waveform. However, the waveform obtained is different where it is attached. May i know where to modify it in order to get the correct the sine waveform?
FYI, i chose the parellel CORDIC algorithm to generate sine waveform. Spec: Phase Acc: 32 Angular Position: 16 Magnitude Precision: 16 Clock rate: 50M desired freq: 1M phi_inc_i: 85899346 Thanks
Honored ContributorThen how do u explain the timing simulation done with the clk 25MHz? The transition changes after the rising edge. Unless you are telling me that the tco will differ much when the clk change from 25MHz to 125MHz..
Honored ContributorUnfortunately, we can't clearly recognize the delay in your various waveforms, because the sending clock edge can't be seen. So we can only guess about possible timing violations. As said, the timing analysis should clearly tell.
Honored ContributorFrom the timing analysis, everything seems fine. However, i just wonder on the tco. It takes 7.334ns.
If that is the case, when running the clk on 25MHz, from the simulaiton, it takes only 1.5ns for the delay instead of 7.334ns. Any reason? Can someone clarify on it? i am not so good on analyze timing analysis. thanks a lotHonored ContributorThe Tco as reported by quartus is meant at the output pins and not the internal registers.
From your simulation diagrams I can estimate Tco = 7.4 ns in either case(25MHz or 125MHz) assuming my eyesight is ok ---|--------------40 ns ------------| ----------| ---|- 8ns --| ----------|Honored ContributorWould it be a problem in hardware implementation if the clk is 125MHz where the previous transition is very near to the next rising clock? If possible, i am trying to use megafunction instead of design a new pipeline CORDIC.
Thanks
