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Altera_Forum's avatar
Altera_Forum
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17 years ago

NCO:out_valid signal

hi. I am using serial CORDIC algorithm to generate the sin waveform. I confused on the out_valid signal when doing the timing simulation.

When the out_valid is high, the data seems not stable, keep changing. The true data wanted is just immediate after the out_valid signal is high or wait for data to be in stable state(out_valid still high)

In my opinion, have to wait for data in stable. What do u all think?

from the attachment,

data wanted is -1469203 or 8127713?

Note: -1469203 is data in stable after -1469211

Thanks

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    You don't show the design clock, but without it, the waveforms are meaningless. The data has to be stable before the next clock edge to allow the data to be latched by the succeeding function in the data path. That's how synchronous FPGA designs work. Consider that dav is intended as a clock enable rather than a clock.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    FvM,

    i attach another waveform that able to see the rising edge clock. After some delay, the fsin_0 signal start to change state. During the changes state of fsin_o, the out_valid signal is high. The problem is the the process of change state of fsin_o stil not finish.

    Question:

    Do I have to take the fsin_o(8127713) once the out_valid signal is high or take the fsin_o complete the state change(-1469203)?

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Yes, as expected. The final value (-1469203) will be latched at the next clock edge.