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Altera_Forum
Honored Contributor
Honored ContributorNCO:out_valid signal
hi. I am using serial CORDIC algorithm to generate the sin waveform. I confused on the out_valid signal when doing the timing simulation. When the out_valid is high, the data seems not stable...
Altera_ForumHonored Contributor
Honored ContributorYou don't show the design clock, but without it, the waveforms are meaningless. The data has to be stable before the next clock edge to allow the data to be latched by the succeeding function in the data path. That's how synchronous FPGA designs work. Consider that dav is intended as a clock enable rather than a clock.
