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Altera_Forum
Honored Contributor
16 years agoNCO:out_valid signal
hi. I am using serial CORDIC algorithm to generate the sin waveform. I confused on the out_valid signal when doing the timing simulation. When the out_valid is high, the data seems not stable...
Altera_Forum
Honored Contributor
16 years agoFvM,
i attach another waveform that able to see the rising edge clock. After some delay, the fsin_0 signal start to change state. During the changes state of fsin_o, the out_valid signal is high. The problem is the the process of change state of fsin_o stil not finish. Question: Do I have to take the fsin_o(8127713) once the out_valid signal is high or take the fsin_o complete the state change(-1469203)? Thanks