Multiply add Block and How to cope with the problem of the lack of ressources

Hi,

In a very general sense:

1) reduce your multiplication at source

2) think of time sharing(TDM) if you can go faster...

3) reduce datawidth to 9 bits or less than 18 bits

4) think of using soft multipliers(horrible on memory)

5) use addition if you can to replace or pre-add then multiply

6) think of any possible premultiplication of results and store in LUT

7) use larger device

8) avoid DSP builder, Do it Yourself

9) give up

Regards

Kaz

Thanks for reply,

Are you suggesting me to live Dsp Builder and return to VhDL on Quartus II?

What TDM is about?

Reducing the datawidth will damage the precision.

Regards

Dzonaser

Hi,

Well, hand-crafting FPGA is by far best for resource. Tools like DSP builder are not that mature yet...but may accelerate the design in some cases or may make it worse producing a pile of garbage.

TDM is time sharing i.e. if I can run at say twice data speed then I can have one multiplier do the job in first cycle for one data then same multiplier do the job for next data(this is minimum TDM factor , =2 and can be higher).

Datawidth if say is 19 bits then it will waste a lot since most altera multipliers are of 9bit graininess.

There are some other points:

9) use power of 2 shift to replace multipliers

10) look for zero multiplicand cases. These cases you know the result??

Kaz

Instead of using DSP blocks all the time, you can try using logic elements for some of the multiply and add. If you are using DSP Builder, in the GUI, there should be a section asking how you want to implement your multiply and add... simply choose auto and let the tool decide. If you are running out of DSP Blocks, then it would start using LEs to implement your multipliers...

Of course, reducing your hardware via TDM is always a good idea...

Hi,

Designing a large number of multipliers from logic(as opposed to dedicated) is a recipe for failure(resource,timing). You better avoid this option.

kaz

I've now managed to reduce the design. I'm still on Dsp Builder 6.0.1, Matlab7.0.1 and Stratix II EPS180 development board. I'm faced to another problem: When programming the device, I have wrong results if there is any. I've tried many options. No way!

I also notice that It's always written that the PLL block can't be implemented Whatever its configuration. Designing without the PLL, with the sample time hand written in the blocks, results are still not equal the those obtained in simulation.

Please help!