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Altera_Forum's avatar
Altera_Forum
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17 years ago

Multiply add Block and How to cope with the problem of the lack of ressources

Hi, I'm still using DSP Builder 6.0 on Matlab 7.01. In fact, after analysing , place an route my model, I'm confronted with a lack of ressources in my FPGA on Dsp Board EP2S180. - 222% utiliza...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I've now managed to reduce the design. I'm still on Dsp Builder 6.0.1, Matlab7.0.1 and Stratix II EPS180 development board. I'm faced to another problem: When programming the device, I have wrong results if there is any. I've tried many options. No way!

I also notice that It's always written that the PLL block can't be implemented Whatever its configuration. Designing without the PLL, with the sample time hand written in the blocks, results are still not equal the those obtained in simulation.

Please help!