Occasional ContributorMultiple questions: writing to PCIe TXS port with 64-bit addressing (Cyclone10GX)
I'm attempting to do DMA writes to the TXS port, with 64-bit addressing enabled. A SignalTap trace shows the bus transfers working fine, but data is not appearing in main memory (at least, not where we expect it.)
1) I have 64-bit addressing enabled. My understanding is that this means the address translation table is ignored. Which is to say, the address I'm providing is being used as-is by on the PCIe bus. Is this correct?
2) In the PCIe core configuration/Avalon-MM Settings (in Platform Designer) I have "Address width of accessible PCIe memory space" set to 33 bits. This sets the width of the txs_address to 33. Is this a byte or a word address? I have assumed this must be a word address, so that there are three additional bits being appended to create the byte address. However, I am unnerved when I click on TXS in Platfom designer, and it shows me this:
If it really thinks it's 8-bits per symbol, then it would be looking for a byte address, and that would certainly explain why the data isn't going where we expect. But I don't think it would make any sense to be expecting a byte address on a 64-bit interface. Not sure what to believe here.
Hi,
- Yes, you are right. No translator is needed for 64 bit addressing.
- The TXS port, it is using byte addressing. If you set the address to 33, the memory size that you can access is 2^33 bytes. From the Platform designer, you will see the address range is from 0x0 to 0x1_ffff_ffff when the addressing width is 33 bits.
Regards -SK
