Multiple DDR2 HPC PingPong Scheme

I am using 2 DDR2 HP controller in my design for the pingpong operation.

ddr2_con ddr2_con_inst_a(

...

.phy_clk (dram_clk_a),

.pll_ref_clk (clk_50m),

...

);

ddr2_con ddr2_con_inst_b(

...

.phy_clk (dram_clk_b),

.pll_ref_clk (clk_50m),

...

);

The pll_ref_clk use the same clock source from external oscillator. All other signals of these 2 ddr2_con use separate signal groups except for reset_n.

Then I've had 2 FIFOs connected to the both ends(write/read) of the 2 ddr2_con. As the 2 controllers have to share 1 fifo on each end, they have to mux several signals to the fifo, such as phy_clk->fifo's rdclk, local_wdata_req-> fifo's rdreq.

Becuase the 2 ddr controller have their own pll, phy_clks are from different plls. there is no way not to break the altera recommendation rules. And fifo's rdreq using a muxed signal also seem to violate the Rule S104.

So I am wondering how everyone impeletment multiple ddr controllers and pingpong operation in their designs.