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Honored Contributor
Honored ContributorMultiple DDR2 HPC PingPong Scheme
I am using 2 DDR2 HP controller in my design for the pingpong operation. ddr2_con ddr2_con_inst_a( ... .phy_clk (dram_clk_a), .pll_ref_clk (clk_50m), ... ); ddr2_con dd...
Altera_ForumHonored Contributor
Honored ContributorI found that as of 9.0sp2, the clock sharing wasn't exactly perfect. It was easier and safer for me to just edit the generated files and re-generating the pll for the slave device and then share all the static clock manually.
Basically what AN462 says: but you can share all of the static clocks, but not the reconfigurable ones. So, the clock that you use to interface to the ddr blocks will be the same clock domain, but the clock that the actual interface is running on will be different.
