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Altera_Forum
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16 years ago

Multiple DDR2 HPC PingPong Scheme

I am using 2 DDR2 HP controller in my design for the pingpong operation. ddr2_con ddr2_con_inst_a( ... .phy_clk (dram_clk_a), .pll_ref_clk (clk_50m), ... ); ddr2_con dd...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi

I'm currently trying to do very much the same as you do. However, I'm not gating the two clocks, but I intend to merge them. On a standallone trial setup (two independant DR2 HPC with their own example_driver, but phy_clocks merged to one), this worked quite well so far (I'm using Stratix III). Major point is the clock merging instructions. You can find them in an462 (http://www.altera.com.cn/literature/an/an462.pdf), Table 6. If you're not desperate, dont' try to share DLL.

Hope this helps...