Dear Sirs and Madams, I have some problem with Fir Compiler II. When i set max number of channels 2, Clock Rate 120MHz and Input Sample Rate 60MSPS filter works perfect but when i change input sample rate to 1MSPS the results are invalid. Maybe somebody know something about this? Maybe somebody have working example with multiple channels and single wire? I check on quartus II 15.0 and quartus prime and on arria v and cyclone v devices. Best regards Adam

When you say that the results are "invalid", what exactly do you mean? The input/output signaling will be significantly different if you change the input sample rate. I don't know if you mean that the MATLAB sims are invalid or if the hardware was not behaving. In the latter case, you will need to create signaling in and out that will have quite a few blank spaces when changing from 60MSPS to 1MSPS. That is a ratio of 1/2 to 1/120. I find the info below to be pretty valuable when coming up with interface logic. After compiling the design, you can right-click on the FIR filter and select "Help...". The following info will appear. This happens to be for a 4-channel DUC (interpolation = 2). In your case, I believe you would see something like the following. It can be used as a baseline for interface logic. 60MSPS: <c0><c1> (repeats every 2) 1MSPS: <c0><c1><--><--><--116 more--> (repeats every 120) [FROM MY DESIGN / DUC INT=2]: Input Data Format (Repeats every 48 clock cycles) <c0><c1><c2><c3><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--> Output Data Format (Repeats every 24 clock cycles) <c0><c1><c2><c3><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--><--> If your data looks bad in the simulations, you might need a down/upsample block from simulink to make the FFT, etc look good. Jeff

Dear Sir, thank you for reply. Of course i take care about blank spaces between data as you wrote. When i say invalid i mean that impulse response from filter is invalid. For example coeffs are 1, 5, 5, 5, 5, 5 1 and impuls impuls response is same like coeffs when i set 60MSPS. When i change to 1MSPS the response is invalid only one coefficient value appears. I dont want to use decim or interpolate. Just filter two channels. Of course hardware not behaving. http://www.alteraforum.com/forum/attachment.php?attachmentid=12340&stc=1 Best regards Adam

Dear Sir, thank you for reply. Of course i take care about blank spaces between data as you wrote. When i say invalid i mean that impulse response from filter is invalid. For example coeffs are 1, 5, 5, 5, 5, 5 1 and impuls impuls response is same like coeffs when i set 60MSPS. When i change to 1MSPS the response is invalid only one coefficient value appears. I dont want to use decim or interpolate. Just filter two channels. Of course hardware not behaving. http://www.alteraforum.com/forum/attachment.php?attachmentid=12342&stc=1 Can you show me screen from simulation or signal tap how you control SOP EOP and valid signal? Best regards Adam

when you set data rate that is not same as clock rate you need to raise valid input pulses one every data sample(zero otherwise). e.g. for 1 Msps on 120Mhz clock then you pulse it once every 120 clocks (or once every 60 clocks if two channels).

Dear Sir, i do what you say but there is same problem. Can you Sir upload some screen from simulation or signal tap how to exacly control SOP, EOP and valid sink signals? Maybe i do something wrong. Best Regards Adam

Multichannel Fir Compiler ii problem. | Altera Community

19 Replies

Altera_Forum
Honored Contributor
10 years ago
Yes sop is first channel and eop is last channel. Maybe i can find some examples somwere? Maybe somebody can show me screen how to control signal when i have 120mhz system clock, 1MSPS, two channels? Maybe i need to set something more in quartus?

I make some more test and when i set 120MHZ system clock, 1MSPS sampling and 120 channels results are perfect for all 120 channels. Maybe there is some timing problems?

Best regards
Adam
Altera_Forum
Honored Contributor
10 years ago
I have a similar issue.

I have a 2 channel decimating filter.

Decimate by 5
220 coefficients
system clock is 150MHz
F sample is 1MHz
F out is 200kHz

When I apply an impulse to it i get a single non-zero output value towards the end of the filters delay.

I'm fairly certain I'm correctly driving the valid, sop, and eop lines. (previous similar designs have worked)

I'm currently using Quartus 15.0 (Tried 15.1, had some issues went back to 15.0)
Thinking about it the previous working designs were probably in 14.something.

I'd be interested if you make any progress on this issue.

Paul
Altera_Forum
Honored Contributor
10 years ago
Is your input and coeff scaling correct. I suggest use impulse input at max value(not just 1) due to internal truncation.
Altera_Forum
Honored Contributor
10 years ago
I think this is not truncation problem because when i use 60MSPS in some test results is ok.
Pchittenden can you check results without decimation? I use quartus 15 and 16 but problem is in both.
Still noo progess.
Altera_Forum
Honored Contributor
10 years ago
Ok I recompiled the filter as a single rate filter. (all other parameters the same as before)

It works correctly without decimation.
Altera_Forum
Honored Contributor
10 years ago
I think there is some bug in FIr Compiler when MSPS to clock ratio is high.
Altera_Forum
Honored Contributor
10 years ago
Looks like a bug to me too.

I decided to go back and generate the same filter in Quartus 14.0.
Works correctly, with or without decimation.
Altera_Forum
Honored Contributor
10 years ago
Thanks for info. I just start talking with support so maybe they will give some answers.
Of course i update forum as soon as i get some new information.
I you have some more info please post it.

Regards
Adam
Altera_Forum
Honored Contributor
10 years ago
Dear Sirs,
problem solved with service request help.
Problem was in reset_n signal. After power up filter must be reseted! Also after filter reset we need to wait few clock cycle before we assert sink_SOP signal.

Best regards
Adam

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Multichannel Fir Compiler ii problem.

19 Replies

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