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Altera_Forum
Honored Contributor
10 years agoMultichannel Fir Compiler ii problem.
Dear Sirs and Madams, I have some problem with Fir Compiler II. When i set max number of channels 2, Clock Rate 120MHz and Input Sample Rate 60MSPS filter works perfect but when i change input s...
Altera_Forum
Honored Contributor
10 years agoI have a similar issue.
I have a 2 channel decimating filter. Decimate by 5 220 coefficients system clock is 150MHz F sample is 1MHz F out is 200kHz When I apply an impulse to it i get a single non-zero output value towards the end of the filters delay. I'm fairly certain I'm correctly driving the valid, sop, and eop lines. (previous similar designs have worked) I'm currently using Quartus 15.0 (Tried 15.1, had some issues went back to 15.0) Thinking about it the previous working designs were probably in 14.something. I'd be interested if you make any progress on this issue. Paul