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Altera_Forum
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9 years ago

Multichannel Fir Compiler ii problem.

Dear Sirs and Madams, I have some problem with Fir Compiler II. When i set max number of channels 2, Clock Rate 120MHz and Input Sample Rate 60MSPS filter works perfect but when i change input s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Yes sop is first channel and eop is last channel. Maybe i can find some examples somwere? Maybe somebody can show me screen how to control signal when i have 120mhz system clock, 1MSPS, two channels? Maybe i need to set something more in quartus?

I make some more test and when i set 120MHZ system clock, 1MSPS sampling and 120 channels results are perfect for all 120 channels. Maybe there is some timing problems?

Best regards

Adam