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New ContributorModelsim error on altera_onchip_flash_block - Error: (vsim-3033): Instantiation of 'altera_onchip_flash_block' failed. The design unit was not found.
Hello.
I'm trying to simulate project with getting data from OnChipFlash.
I'm using the Lite edition of Quartus 17.0.2 and ModelSim - INTEL FPGA STARTER EDITION 10.5b.
I create testbench file to simulate the project. I start the simulation using "Tools -> Run Simulation Tool -> RTL Simulation".
When the simulation starts, I get following error on the ModelSim output:
** Error: (vsim-3033) c:/intelfpga_lite/16.1/projects/dac+nios_ltc1668+ad5791_fsm/db/ip/onchipflash/submodules/altera_onchip_flash.v(305): Instantiation of 'altera_onchip_flash_block' failed. The design unit was not found.
# Time: 0 ps Iteration: 0 Instance: /AC_main_tb/main_inst/sin_data/onchip_flash_0 File: c:/intelfpga_lite/16.1/projects/dac+nios_ltc1668+ad5791_fsm/db/ip/onchipflash/submodules/altera_onchip_flash.v
When I comments the OnChipFlash module everything works well, but without extracting data from flash.
File altera_onchip_flash_block.v do not opened, because is encrypted file.
I find similar post on forum:
I tried to perform the actions as written in the post above with the substitution of my names:
1) Open the qsys files, generate the simulation model, generate -> generate hdl
2) Open modesim, cd to directory where the msim_setup.tcl
source msim_setup.tcl
3) ld
4) open the msim_setup.tcl and modify the top level from "OnChipFlash" to "AC_meas_tb"
6) add the following lines under vlog in "alias com" section, at the end, in this order:
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/main.v"
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/AC_meas_tb.v"
7) ld again.
I get following error:
Error: (vlog-7) Failed to open design unit file "./..//main.v" in read mode.
# No such file or directory. (errno = ENOENT)
If I start simulation using "Tools -> Run Simulation Tool -> RTL Simulation" I get error Error: (vsim-3033) .....altera_onchip_flash.v(305): Instantiation of 'altera_onchip_flash_block' failed. The design unit was not found.
At this point, any help would be greatly appreciated, or workaround as well.
Thanks, Aleksey
You make the AC_meas_tb as the testbench. Can you check inside the AC_meas_tb.v files, what is your module name there? currently, the tools are complaining the testbench issue.
22 Replies
KennyT_alteraSuper Contributor
This seems to be the setting of the modelsim got some problem. The modelsim of the setting is modelsim.ini, what you can do is try to backup this file and let the modelsim recreate it from scratch.
AVovkHello KennyT_Intel.
I deleted the modelsim.ini file, ModelSim recreated it exactly the same and this did not solve the problem.
After a little thought, I decided to add lines to the "alias com" section with modules on which the ModelSim gives errors:
eval vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/../../receiving_from_PC.v"
etc.
This solve the problem.
Thanks!
- AVovk
Again the problem.
Data from flash memory is not retrieved, data is always in logical 1.
Modelsim writes the following in log:
# ** Warning: (vsim-3017) ./../submodules/altera_onchip_flash.v(297): [TFMPC] - Too few port connections. Expected 18, found 17.
# Time: 0 ps Iteration: 0 Instance: /AC_meas_tb/main_inst/sin_data/onchip_flash_0/altera_onchip_flash_block File: nofile
# ** Warning: (vsim-3722) ./../submodules/altera_onchip_flash.v(297): [TFMPC] - Missing connection for port 'bgpbusy'.
# ** Warning: (vsim-3017) <protected>(<protected>): [TFMPC] - Too few port connections. Expected <protected>, found <protected>.
# Time: 0 ps Iteration: 0 Protected: /AC_meas_tb/main_inst/sin_data/onchip_flash_0/altera_onchip_flash_block/<protected>/<protected>/<protected>/<protected>/<protected>/<protected> File: nofile
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
# ** Warning: (vsim-3722) <protected>(<protected>): [TFMPC] - Missing connection for port '<protected>'.
These are the only compilation warnings.
All data is protected. Therefore, there is no retrieval of them?
- AVovk
I thought that the problems were only with the simulation, since in addition to the data, all other signals are formed as it should, judging by the simulator.
After programming, the project works the same way - reading a flash always returns FFFFFFFF.
- KennyT_altera
Does this issue happened intermittently or consistently?
- AVovk
After I started the simulation of the project with the OnchipFlash module used (thank you for your help), the simulator shows that FFFFFF is always returned from the flash. Having programmed the project, I was convinced of it, observing the data on an oscilloscope.
- AVovk
I searched the Internet for an example of working with Flash memory, thinking that there was a mistake somewhere in my project and therefore FFFFF was always read from Flash. On FpgaCloud, I found a project like this:
I started the simulation and saw that FFFFF is always read from Flash. This project was created by Altera (Intel), I am sure that there is no error in it.
Why is FFFFF always read from Flash?
PS I am using Quartus 17.0.
- KennyT_altera
Can u open a new thread on this? this seem to be different issue from the original one.
- AVovk
I found the answer why FFFFF is always read from flash memory. The answer is simple: I always used a SOF file for programming, but when flash memory is used, I need to program a POF file.
PS: I apologize for such a long feedback
