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Altera_Forum's avatar
Altera_Forum
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18 years ago

Microtronix non-Avalon multi-port memory controller

All,

Here are the datasheets of Microtronix' IPs:

- High Performance Avalon Multi-Port SDRAM Memory Controller IP core, and

- High Performance Streaming Multi-Port SDRAM Memory Controller IP core (NEW!).

If you have any questions, please contact Microtronix (http://www.microtronix.com).

Best Regards,

--jmv

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I was wondering if anyone here has tried the Microtronix non-avalon multi-port controller? I am having a strange issue with it.

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I suggest that you contact Microtronix to discuss your strange issue.

    --jmv
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hi,

    what is meant by "Intelligent SDRAM burst caching minimizes wait-states"?:confused:

    Are the request (RD or WR) resorted, so that there are a minimum of bank precharges and the controller tries to write (or read) the longest possible burst length supported by the memory?

    Regards

    Christian
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hi,

    we have tried the Microtronix non-avalon multi-port controller. And in our evaluation phase we had no problems with the IP-Core. We were also able to reach the promised speed in a test implementation.

    We didn't run a design in hardware. We verified the functionality in simulation to find out if it meets our requirements.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hello Christian,

    You're right. The FIFOs are concatenating individual port accesses into one long access to the SDRAM memory. This minimizes the total CAS latency compared to single transfers.

    Best Regards,

    Marco