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Altera_Forum
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19 years ago

Microtronix non-Avalon multi-port memory controller

All, Here are the datasheets of Microtronix' IPs: - High Performance Avalon Multi-Port SDRAM Memory Controller IP core, and - High Performance Streaming Multi-Port SDRAM Memory Controller ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

Hi,

what is meant by "Intelligent SDRAM burst caching minimizes wait-states"?:confused:

Are the request (RD or WR) resorted, so that there are a minimum of bank precharges and the controller tries to write (or read) the longest possible burst length supported by the memory?

Regards

Christian