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Honored Contributor
Honored ContributorMicrotronix non-Avalon multi-port memory controller
All, Here are the datasheets of Microtronix' IPs: - High Performance Avalon Multi-Port SDRAM Memory Controller IP core, and - High Performance Streaming Multi-Port SDRAM Memory Controller ...
Altera_ForumHonored Contributor
Honored ContributorHello Christian,
You're right. The FIFOs are concatenating individual port accesses into one long access to the SDRAM memory. This minimizes the total CAS latency compared to single transfers. Best Regards, Marco
