Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Microtronix non-Avalon multi-port memory controller

All, Here are the datasheets of Microtronix' IPs: - High Performance Avalon Multi-Port SDRAM Memory Controller IP core, and - High Performance Streaming Multi-Port SDRAM Memory Controller ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hello Christian,

You're right. The FIFOs are concatenating individual port accesses into one long access to the SDRAM memory. This minimizes the total CAS latency compared to single transfers.

Best Regards,

Marco