Memory Mapped Interconnect Reset Net Polarity Conflict

I have developed a simple client Avalon Memory Mapped Interface custom IP block. The MM interconnect block automatically generated a width adapter component that is causing an LNT-30023 - Reset Nets with Polarity Conflict DRC. It is not affecting the functionality of my custom MM block, but I am still interested in understanding the root cause of this issue. Details to follow, thank you in advance for any help.

Custom Avalon Memory Mapped Interface consists of the following signals:

• clk
• reset_n
• [7:0] writedata
• write
• [7:0] address
• Various conduit signals

The master is the JTAG to Avalon Master Bridge which defaults to have 32bit address and writedata signals. For this configuration a merlin width adapter is automatically generated in the mm_interconnect block of the platform system designer. 

Both the custom IP block and the JTAG to Avalon Master Bridge are connected to an low-assert (reset_n) Reset Bridge IP Block. The custom IP block is configured to be an low-assert reset. I was under the impression all generated MM interconnect IP would inherit the low-assert reset.

Instead my Design Assistant Summary declares the following DRC error: LNT-30023 - Reset Nets with Polarity Conflict. The detailed description is as follows, where <my_block> is a placeholder for my custom block name:

• Driver: u0|mm_interconnect_0|<my_block>_avalon_slave_0_cmd_width_adapter|use_reg
• Non-inverted signal: u0|mm_interconnect_0|<my_block>_avalon_slave_0_cmd_width_adapter|data_reg[16]|SCLR
• Inverted Signal:  u0|mm_interconnect_0|<my_block>_avalon_slave_0_cmd_width_adapter|address_reg[1]|SCLR