LVDS and PLL IP on DE1

Hello,

I am trying to implement a LVDS to RGB converter in the DE1 board.

I am using the LVDS and PLL IP Megafunction. I used as a template the "Design Example 2: Cyclone II ALTLVDS Using External PLL Option" from the ALTLVDS Megafunction User Guide. I changed the FPGA used because it's not the exact same one as in the DE1 board.

Then when I am assigning the pins to the expansion header of the DE1 board (I also precise in the "I/O Standard": LVDS), Quartus Fitter gives me the following error:

"Error: Can't place PLL "lvds_pll:inst2|altpll:altpll_component|pll" -- I/O pin "ref_clock" (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device"

Can somebody explain to me what this error means and how I can solve it?

Thank you in advance,

Meach