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Altera_Forum's avatar
Altera_Forum
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16 years ago

LVDS and PLL IP on DE1

Hello, I am trying to implement a LVDS to RGB converter in the DE1 board. I am using the LVDS and PLL IP Megafunction. I used as a template the "Design Example 2: Cyclone II ALTLVDS Using Ext...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

To use LVDS with a development board, the board needs to have a LVDS interface.

IIRC, the Cyclone III starter kit has.

VCCIO is the voltage that powers the I/O elements. The maximum LVDS signal voltage is 2.4V but the FPGA I/O elements must be powered with 2.5V for LVDS.

Trying to use LVDS with 1.8V VCCIO is not document anywhere, AFAIK, and it will problably not work.