L- and H-tile Avalon® Streaming Stratix 10 PCIe IP Core - Access to Root Port Configuration Space
Hello,
for my design on a Stratix-10 MX FPGA I use the L- and H-tile Avalon Streaming IP-Core configured as Root-Port.
As per PCIe-Specifiaction, a root-port has a PCI Configuration Space Header of Type-1 which should be accessible with PCIe-Configuration Transactions of Type-0.
However, when issuing Configuration Transactions of Type-0 to the Root-Port via the Avalon Streaming Interface, the Root-Port forwards them to the Device on the other end of the PCIe-Lane (serial interface).
The spec states, that only Configuration Transactions of Type-1 should be forwarded to the Link, if the Bus Number of the Completer-ID in the TLP Header falls in the range (Secondary Bus Number, Subordinate Bus Number] of the Root-Ports Configuration Space Header. Configuration Transactions of Type-1 should be converted to Type-0, if the Bus Number of the Completer-ID in the TLP Header equals the Secondary Bus Number of the Roots Configuration Space Header.
Hence my question: Is a configuration of the Root-Ports Configuration Space neccessary , such as setting the Memory Base- and Limit Registers, Subordinary and Secondary Bus Number Registers, Command Register etc.?
If so, how do I properly access the Root-Ports Configuration Space?
Thanks in advance!
