Forum Discussion
L- and H-tile Avalon® Streaming Stratix 10 PCIe IP Core - Access to Root Port Configuration Space
Hello, for my design on a Stratix-10 MX FPGA I use the L- and H-tile Avalon Streaming IP-Core configured as Root-Port. As per PCIe-Specifiaction, a root-port has a PCI Configuration Space Header of...
Wincent_Altera
Regular Contributor
Regular ContributorHi,
I wish to follow up with you about this case.
Do you have any further questions on this matter ?
Else I would like to have your permission to close this forum ticket
Regards,
Wincent_Intel
