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Anonymous

2 years ago

L- and H-tile Avalon® Streaming Stratix 10 PCIe IP Core - Access to Root Port Configuration Space

Hello, for my design on a Stratix-10 MX FPGA I use the L- and H-tile Avalon Streaming IP-Core configured as Root-Port. As per PCIe-Specifiaction, a root-port has a PCI Configuration Space Header of...

Pcie

Wincent_Altera

Regular Contributor

2 years ago

Hi,

Root Port Stratix 10 , you can refer to the design example

https://www.rocketboards.org/foswiki/Projects/Stratix10PCIeRootPortWithMSI?elq_cid=4474485_ts1687308874155&erpm_id=10887203_ts1687308874155

Let me know if you need any further clarification.

Regards,

Wincent_Intel

Forum Discussion

L- and H-tile Avalon® Streaming Stratix 10 PCIe IP Core - Access to Root Port Configuration Space

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